`timescale 1ns / 1ps
/*
Description: 
*/
//////////////////////////////////////////////////////////////////////////////////

module uidbuf#(
parameter  integer                    ENABLE_WRITE   = 1    ,//使能写通道 
parameter  integer                    ENABLE_READ    = 1    ,//使能读通道 

parameter  integer                    AXI_DATA_WIDTH = 128  ,//AXI总线数据位宽 
parameter  integer                    AXI_ADDR_WIDTH = 32   ,//AXI总线地址位宽 

parameter  integer                    W_BUFDEPTH     = 2048 ,//写通道AXI设置FIFO缓存大小 
parameter  integer                    W_DATAWIDTH    = 32   ,//写通道AXI设置数据位宽大小
parameter  [AXI_ADDR_WIDTH -1'b1: 0]  W_BASEADDR     = 0    ,//写通道设置内存起始地址 
parameter  integer                    W_DSIZEBITS    = 24   ,//写通道设置缓存数据的增量地址大小，用于FDMA DBUF 计算帧缓存起始地址 
parameter  integer                    W_XSIZE        = 1920 ,//写通道设置X方向的数据大小，代表了每次FDMA 传输的数据长度 
parameter  integer                    W_XSTRIDE      = 1920 ,//写通道设置X方向的Stride值，主要用于图形缓存应用
parameter  integer                    W_YSIZE        = 1080 ,//写通道设置Y方向值，代表了进行了多少次XSIZE传输
parameter  integer                    W_XDIV         = 2    ,//写通道对X方向数据拆分为XDIV次传输，减少FIFO的使用 
parameter  integer                    W_BUFSIZE      = 3    ,//写通道设置帧缓存大小，目前最大支持128帧，可以修改参数支持更缓存数 

parameter  integer                    R_BUFDEPTH     = 2048 ,//读通道AXI设置FIFO缓存大小 
parameter  integer                    R_DATAWIDTH    = 32   ,//读通道AXI设置数据位宽大小
parameter  [AXI_ADDR_WIDTH -1'b1: 0]  R_BASEADDR     = 0    ,//读通道设置内存起始地址
parameter  integer                    R_DSIZEBITS    = 24   ,//读通道设置缓存数据的增量地址大小，用于FDMA DBUF 计算帧缓存起始地址 
parameter  integer                    R_XSIZE        = 1920 ,//读通道设置X方向的数据大小，代表了每次FDMA 传输的数据长度 
parameter  integer                    R_XSTRIDE      = 1920 ,//读通道设置X方向的Stride值，主要用于图形缓存应用
parameter  integer                    R_YSIZE        = 1080 ,//读通道设置Y方向值，代表了进行了多少次XSIZE传输
parameter  integer                    R_XDIV         = 2    ,//读通道对X方向数据拆分为XDIV次传输，减少FIFO的使用
parameter  integer                    R_BUFSIZE      = 3     //读通道设置帧缓存大小，目前最大支持128帧，可以修改参数支持更缓存数 
)
(
input wire                                  ui_clk          ,//和FDMA AXI总线时钟一致
input wire                                  ui_rstn         ,//和FDMA AXI复位一致
//------------W_FIFO----------------
input wire                                  W_wclk_i        ,//写FIFO写数据接口时钟
input wire                                  W_fifo_rst      ,//写通道FIFO复位，高有效
input wire                                  W_FS_i          ,//写FIFO写数据接口同步信号，对于非视频帧一般设置为1
input wire                                  W_FS_i_clk      ,//W_FS_i信号时钟域下时钟 
input wire                                  W_wren_i        ,//写FIFO写数据使能 
input wire     [W_DATAWIDTH-1'b1 : 0]       W_data_i        ,//写FIFO写数据 
output reg     [7   :0]                     W_sync_cnt_o =0 ,//写通道BUF帧同步输出  
input  wire    [7   :0]                     W_buf_i         ,//写通道BUF帧同步输入 
output wire                                 W_full          ,//FIFO写满标志
//----------fdma signals write-------       
output wire    [AXI_ADDR_WIDTH-1'b1: 0]     fdma_waddr      ,//FDMA写通道地址
output wire                                 fdma_wareq      ,//FDMA写通道请求
output wire    [15  :0]                     fdma_wsize      ,//FDMA写通道一次FDMA的传输大小                                       
input  wire                                 fdma_wbusy      ,//FDMA处于BUSY状态，AXI总线正在写操作    		
output wire    [AXI_DATA_WIDTH-1'b1:0]      fdma_wdata      ,//FDMA写数据
input  wire                                 fdma_wvalid     ,//FDMA写有效
output wire                                 fdma_wready     ,//FDMA写准备好，用户可以写数据
output reg     [7   :0]                     fmda_wbuf =0    ,//FDMA的写帧缓存号输出 
output wire                                 fdma_wirq       ,//FDMA一次写完成的数据传输完成后，产生中断
//------------R_FIFO-----------------
input  wire                                 R_rclk_i        ,//读FIFO读数据接口时钟
input  wire                                 R_fifo_rst      ,//读通道FIFO复位，高有效
input  wire                                 R_FS_i          ,//读FIFO读数据接口同步信号，对于非视频帧一般设置1 
input  wire                                 R_FS_i_clk      ,//R_FS_i信号时钟域下时钟 
input  wire                                 R_rden_i        ,//读FIFO读数据使能
output wire    [R_DATAWIDTH-1'b1 : 0]       R_data_o        ,//读FIFO读数据 
output reg     [7   :0]                     R_sync_cnt_o =0 ,//读通道BUF帧同步输出
input  wire    [7   :0]                     R_buf_i         ,//写通道BUF帧同步输入 
output wire                                 R_empty         ,//读FIFO读空标志
//----------fdma signals read--------  
output wire    [AXI_ADDR_WIDTH-1'b1: 0]     fdma_raddr      ,//FDMA读通道地址 
output wire                                 fdma_rareq      ,//FDMA读通道请求 
output wire    [15: 0]                      fdma_rsize      ,//FDMA读通道一次FDMA的传输大小                                        
input  wire                                 fdma_rbusy      ,//FDMA处于BUSY状态，AXI总线正在读操作    			
input  wire    [AXI_DATA_WIDTH-1'b1:0]      fdma_rdata      ,//FDMA读数据 
input  wire                                 fdma_rvalid     ,//FDMA 读有效
output wire                                 fdma_rready     ,//FDMA读准备好，用户可以写数据
output reg     [7  :0]                      fmda_rbuf =0    ,//FDMA的读帧缓存号输出 
output wire                                 fdma_rirq	       //FDMA一次读完成的数据传输完成后，产生中断
);    

//计算Log2 
function integer clog2;
  input integer value;
  begin 
    value = value-1;
    for (clog2=0; value>0; clog2=clog2+1)
      value = value>>1;
  end 
endfunction

//FDMA读写状态机的状态值  
localparam S_IDLE  =  2'd0;  
localparam S_RST   =  2'd1;  
localparam S_DATA1 =  2'd2;   
localparam S_DATA2 =  2'd3; 

// 通过设置读/写使能，生成不同的块
generate  
  if(ENABLE_WRITE == 1)begin : FDMA_WRITE_ENABLE

    localparam WFIFO_DEPTH            = W_BUFDEPTH                                              ;//写FIFO深度    
    localparam W_WR_DATA_COUNT_WIDTH  = clog2(WFIFO_DEPTH)+1                                    ;//计算FIFO的写通道位宽
    localparam W_RD_DATA_COUNT_WIDTH  = clog2(WFIFO_DEPTH*W_DATAWIDTH/AXI_DATA_WIDTH)+1         ;//clog2(WFIFO_DEPTH/(AXI_DATA_WIDTH/W_DATAWIDTH))+1;

    localparam WYBUF_SIZE             = (W_BUFSIZE - 1'b1)                                      ;//写通道需要完成多少次XSIZE操作 
    localparam WY_BURST_TIMES         = (W_YSIZE*W_XDIV)                                        ;//写通道需要完成的FDMA burst 操作次数，XDIV用于把XSIZE分解多次传输
    localparam FDMA_WX_BURST          = (W_XSIZE*W_DATAWIDTH/AXI_DATA_WIDTH)/W_XDIV             ;//FDMA BURST 一次的大小 
    localparam WX_BURST_ADDR_INC      = (W_XSIZE*(W_DATAWIDTH/8))/W_XDIV                        ;//FDMA每次burst之后的地址增加 
    localparam WX_LAST_ADDR_INC       = (W_XSTRIDE-W_XSIZE)*(W_DATAWIDTH/8) + WX_BURST_ADDR_INC ;//根据stride值计算出来最后一次地址 

    reg                                     fdma_wareq_r  = 1'b0;
    reg                                     W_FIFO_Rst    = 1'b0; 
    wire                                    W_FS                ;
    reg [1 :0]                              W_MS          =    0;//状态机状态值寄存器 
    reg [W_DSIZEBITS-1'b1:0]                W_addr        =    0; 
    reg [15:0]                              W_bcnt        =    0; 
    wire[W_RD_DATA_COUNT_WIDTH-1'b1 :0]     W_rcnt              ;
    reg                                     W_REQ         =    0; 
    reg [5 :0]                              wirq_dly_cnt  =    0;
    reg [3 :0]                              wdiv_cnt      =    0;
    reg [7 :0]                              wrst_cnt      =    0;
    reg [7 :0]                              fmda_wbufn          ;
    reg [1:0]                               W_MS_r        =    0;
    wire                                    wirq          = fdma_wirq;

    assign fdma_wready                      = 1'b1                            ;
    assign fdma_wsize                       = FDMA_WX_BURST                   ;
    assign fdma_wirq                        = (wirq_dly_cnt>0)                ;
    assign fdma_waddr                       = W_BASEADDR + {fmda_wbufn,W_addr};
    assign fdma_wareq                       = fdma_wareq_r                    ;

    //每次FDMA DBUF 完成一帧数据传输后，产生中断，这个中断持续60个周期的uiclk,这里的延迟必须足够ZYNQ IP核识别到这个中断
    always @(posedge ui_clk) W_MS_r <= W_MS;
    always @(posedge ui_clk) begin
        if(ui_rstn == 1'b0)begin
            wirq_dly_cnt <= 6'd0;
            fmda_wbuf <=0;
        end
        else if((W_MS_r == S_DATA2) && (W_MS == S_IDLE))begin
            wirq_dly_cnt <= 60;
            fmda_wbuf <= fmda_wbufn;
        end
        else if(wirq_dly_cnt >0)
            wirq_dly_cnt <= wirq_dly_cnt - 1'b1;
    end

    //时钟域转换，src_clk >= dest_clk ,时钟可为异步
    xpm_cdc_single #(
       .DEST_SYNC_FF  (4), // DECIMAL; range: 2-10
       .INIT_SYNC_FF  (0), // DECIMAL; 0=disable simulation init values, 1=enable simulation init values
       .SIM_ASSERT_CHK(0), // DECIMAL; 0=disable simulation messages, 1=enable simulation messages
       .SRC_INPUT_REG (1)  // DECIMAL; 0=do not register input, 1=register input
    )
    xpm_cdc_single_inst (
       .dest_out(W_FS       ),  
       .dest_clk(ui_clk     ),
       .src_clk (W_FS_i_clk ),
       .src_in  (W_FS_i     )      
    );

     always @(posedge ui_clk) begin
        if(!ui_rstn)begin
            W_MS         <= S_IDLE;
            W_FIFO_Rst   <= 0;
            W_addr       <= 0;
            W_sync_cnt_o <= 0;
            W_bcnt       <= 0;
            wrst_cnt     <= 0;
            wdiv_cnt     <= 0;
            fmda_wbufn    <= 0;
            fdma_wareq_r <= 1'd0;
        end   
        else begin
          case(W_MS)
            S_IDLE:begin
              W_addr <= 0;
              W_bcnt <= 0;
              wrst_cnt <= 0;
              wdiv_cnt <=0;
              if(W_FS) begin
                W_MS <= S_RST;
                if(W_sync_cnt_o < WYBUF_SIZE)
                    W_sync_cnt_o <= W_sync_cnt_o + 1'b1; 
                else 
                    W_sync_cnt_o <= 0;  
              end
           end
           S_RST:begin
               fmda_wbufn <= W_buf_i;
              //  wrst_cnt <= wrst_cnt + 1'b1;
              //  if((FIFO_RST_ENABLE == 1) && (wrst_cnt < 40))
              //       W_FIFO_Rst <= 1;
              //  else if((FIFO_RST_ENABLE == 1) && (wrst_cnt < 100))
              //       W_FIFO_Rst <= 0;
               if(fdma_wirq == 1'b0) begin
                    W_MS <= S_DATA1;
               end
           end
            S_DATA1:begin 
              if(fdma_wbusy == 1'b0 && W_REQ )begin
                 fdma_wareq_r  <= 1'b1; 
              end 
              else if(fdma_wbusy == 1'b1) begin
                 fdma_wareq_r  <= 1'b0;
                 W_MS    <= S_DATA2;
              end          
             end
            S_DATA2:begin 
                if(fdma_wbusy == 1'b0)begin
                    if(W_bcnt == WY_BURST_TIMES - 1'b1)
                        W_MS <= S_IDLE;
                    else begin
                        if(wdiv_cnt < W_XDIV - 1'b1)begin
                            W_addr <= W_addr +  WX_BURST_ADDR_INC;  
                            wdiv_cnt <= wdiv_cnt + 1'b1;
                         end
                        else begin
                            W_addr <= W_addr + WX_LAST_ADDR_INC;
                            wdiv_cnt <= 0;
                        end
                        W_bcnt <= W_bcnt + 1'b1;
                        W_MS    <= S_DATA1;
                    end 
                end
             end
             default: W_MS <= S_IDLE; 
           endcase
        end
     end 


    wire W_rbusy;
    always@(posedge ui_clk)     
         W_REQ  <= (W_rcnt > FDMA_WX_BURST - 2)&&(~W_rbusy); 

    xpm_fifo_async # (
      .FIFO_MEMORY_TYPE          ("auto"),           //string; "auto", "block", or "distributed";
      .ECC_MODE                  ("no_ecc"),         //string; "no_ecc" or "en_ecc";
      .RELATED_CLOCKS            (0),                //positive integer; 0 or 1
      .FIFO_WRITE_DEPTH          (WFIFO_DEPTH),     //positive integer
      .WRITE_DATA_WIDTH          (W_DATAWIDTH),               //positive integer
      .WR_DATA_COUNT_WIDTH       (W_WR_DATA_COUNT_WIDTH),               //positive integer
      .PROG_FULL_THRESH          (20),               //positive integer
      .FULL_RESET_VALUE          (0),                //positive integer; 0 or 1
      .USE_ADV_FEATURES          ("0707"),           //string; "0000" to "1F1F"; 
      .READ_MODE                 ("fwft"),            //string; "std" or "fwft";
      .FIFO_READ_LATENCY         (0),                //positive integer;
      .READ_DATA_WIDTH           (AXI_DATA_WIDTH),               //positive integer
      .RD_DATA_COUNT_WIDTH       (W_RD_DATA_COUNT_WIDTH),               //positive integer
      .PROG_EMPTY_THRESH         (10),               //positive integer
      .DOUT_RESET_VALUE          ("0"),              //string
      .CDC_SYNC_STAGES           (2),                //positive integer
      .WAKEUP_TIME               (0)                 //positive integer; 0 or 2;
    ) xpm_fifo_W_inst (
          .rst              (W_fifo_rst),//clk domain : wr_clk
          .wr_clk           (W_wclk_i),
          .wr_en            (W_wren_i),
          .din              (W_data_i),
          .full             (W_full),
          .overflow         (),
          .prog_full        (),
          .wr_data_count    (),
          .almost_full      (),
          .wr_ack           (),
          .wr_rst_busy      (),
          .rd_clk           (ui_clk),
          .rd_en            (fdma_wvalid),
          .dout             (fdma_wdata),
          .empty            (),
          .underflow        (),
          .rd_rst_busy      (W_rbusy),
          .prog_empty       (),
          .rd_data_count    (W_rcnt),
          .almost_empty     (),
          .data_valid       (W_dvalid),
          .sleep            (1'b0),
          .injectsbiterr    (1'b0),
          .injectdbiterr    (1'b0),
          .sbiterr          (),
          .dbiterr          ()
    );
  end
  else begin : FDMA_WRITE_DISABLE
    //禁用写使能，fdma总线赋0
    assign fdma_waddr   = 0;
    assign fdma_wareq   = 0;
    assign fdma_wsize   = 0;                                   	
    assign fdma_wdata   = 0;
    assign fdma_wready  = 0;
    assign fdma_wirq    = 0;	
    assign W_full       = 0;
  end
endgenerate


generate  
  if(ENABLE_READ == 1) begin : FDMA_READ
    localparam RYBUF_SIZE           = (R_BUFSIZE - 1'b1);
    localparam RY_BURST_TIMES       = (R_YSIZE*R_XDIV);
    localparam FDMA_RX_BURST        = (R_XSIZE*R_DATAWIDTH/AXI_DATA_WIDTH)/R_XDIV;
    localparam RX_BURST_ADDR_INC    = (R_XSIZE*(R_DATAWIDTH/8))/R_XDIV;
    localparam RX_LAST_ADDR_INC     = (R_XSTRIDE-R_XSIZE)*(R_DATAWIDTH/8) + RX_BURST_ADDR_INC;

    localparam RFIFO_DEPTH = R_BUFDEPTH*R_DATAWIDTH/AXI_DATA_WIDTH;//R_BUFDEPTH/(AXI_DATA_WIDTH/R_DATAWIDTH);
    localparam R_WR_DATA_COUNT_WIDTH = clog2(RFIFO_DEPTH)+1;
    localparam R_RD_DATA_COUNT_WIDTH = clog2(R_BUFDEPTH)+1;

    reg                                     fdma_rareq_r= 1'b0    ;
    reg                                     R_FIFO_Rst=0          ; 
    wire                                    R_FS                  ;
    reg [1 :0]                              R_MS=0                ; 
    reg [R_DSIZEBITS-1'b1:0]                R_addr=0              ; 
    reg [15:0]                              R_bcnt=0              ; 
    wire[R_WR_DATA_COUNT_WIDTH-1'b1 :0]     R_wcnt                ;
    reg                                     R_REQ=0               ; 
    reg [5 :0]                              rirq_dly_cnt =0       ;
    reg [3 :0]                              rdiv_cnt =0           ;
    reg [7 :0]                              rrst_cnt =0           ;
    reg [7 :0]                              fmda_rbufn            ;

    assign fdma_rsize   = FDMA_RX_BURST                           ;
    assign fdma_rirq    = (rirq_dly_cnt>0)                        ;
    assign fdma_raddr   = R_BASEADDR + {fmda_rbufn,R_addr}        ;
    assign fdma_rready  = 1'b1                                    ;
    assign fdma_rareq   = fdma_rareq_r                            ;
    //每次FDMA DBUF 完成一帧数据传输后，产生中断，这个中断持续60个周期的uiclk,这里的延迟必须足够ZYNQ IP核识别到这个中断
    reg [1:0] R_MS_r =0;
    always @(posedge ui_clk) R_MS_r <= R_MS;
    always @(posedge ui_clk) begin
        if(ui_rstn == 1'b0)begin
            rirq_dly_cnt <= 6'd0;
            fmda_rbuf <=0;
        end
        else if((R_MS_r == S_DATA2) && (R_MS == S_IDLE))begin
            rirq_dly_cnt <= 60;
            fmda_rbuf <= fmda_rbufn;
        end
        else if(rirq_dly_cnt >0)
            rirq_dly_cnt <= rirq_dly_cnt - 1'b1;
    end


    //时钟域转换，src_clk >= dest_clk ,时钟可为异步
    xpm_cdc_single #(
       .DEST_SYNC_FF  (4), // DECIMAL; range: 2-10
       .INIT_SYNC_FF  (0), // DECIMAL; 0=disable simulation init values, 1=enable simulation init values
       .SIM_ASSERT_CHK(0), // DECIMAL; 0=disable simulation messages, 1=enable simulation messages
       .SRC_INPUT_REG (1)  // DECIMAL; 0=do not register input, 1=register input
    )
    xpm_cdc_single_inst (
       .dest_out(R_FS       ),  
       .dest_clk(ui_clk     ),
       .src_clk (R_FS_i_clk ),
       .src_in  (R_FS_i     )      
    );

     always @(posedge ui_clk) begin
       if(!ui_rstn)begin
            R_MS          <= S_IDLE;
            R_FIFO_Rst   <= 0;
            R_addr       <= 0;
            R_sync_cnt_o <= 0;
            R_bcnt       <= 0;
            rrst_cnt     <= 0;
            rdiv_cnt      <= 0;
            fmda_rbufn    <= 0;
            fdma_rareq_r  <= 1'd0;
        end   
        else begin
          case(R_MS)
            S_IDLE:begin
              R_addr <= 0;
              R_bcnt <= 0;
              rrst_cnt <= 0;
              rdiv_cnt <=0;
              if(R_FS) begin
                R_MS <= S_RST;
                if(R_sync_cnt_o < RYBUF_SIZE)
                    R_sync_cnt_o <= R_sync_cnt_o + 1'b1; 
                else 
                    R_sync_cnt_o <= 0;  
              end
           end
           S_RST:begin
               fmda_rbufn <= R_buf_i;
              //  rrst_cnt <= rrst_cnt + 1'b1;
              //  if((FIFO_RST_ENABLE == 1) && (rrst_cnt < 40))
              //       R_FIFO_Rst <= 1;
              //  else if((FIFO_RST_ENABLE == 1) && (rrst_cnt < 100))
              //       R_FIFO_Rst <= 0;
               if(fdma_rirq == 1'b0) begin
                    R_MS <= S_DATA1;
               end
           end
           S_DATA1:begin 
             if(fdma_rbusy == 1'b0 && R_REQ)begin
                fdma_rareq_r  <= 1'b1;  
             end
             else if(fdma_rbusy == 1'b1) begin
                fdma_rareq_r  <= 1'b0;
                R_MS    <= S_DATA2;
             end         
            end
            S_DATA2:begin 
                if(fdma_rbusy == 1'b0)begin
                    if(R_bcnt == RY_BURST_TIMES - 1'b1)
                        R_MS <= S_IDLE;
                    else begin
                        if(rdiv_cnt < R_XDIV - 1'b1)begin
                            R_addr <= R_addr +  RX_BURST_ADDR_INC;  
                            rdiv_cnt <= rdiv_cnt + 1'b1;
                         end
                        else begin
                            R_addr <= R_addr + RX_LAST_ADDR_INC;
                            rdiv_cnt <= 0;
                        end
                        R_bcnt <= R_bcnt + 1'b1;
                        R_MS    <= S_DATA1;
                    end 
                end
             end
             default:R_MS <= S_IDLE;
          endcase
       end
    end 

    wire R_wbusy;
    always@(posedge ui_clk)      
         R_REQ  <= (R_wcnt < FDMA_RX_BURST - 2)&&(~R_wbusy);


    xpm_fifo_async # (
      .FIFO_MEMORY_TYPE          ("auto"),           //string; "auto", "block", or "distributed";
      .ECC_MODE                  ("no_ecc"),         //string; "no_ecc" or "en_ecc";
      .RELATED_CLOCKS            (0),                //positive integer; 0 or 1
      .FIFO_WRITE_DEPTH          (RFIFO_DEPTH),     //positive integer
      .WRITE_DATA_WIDTH          (AXI_DATA_WIDTH),               //positive integer
      .WR_DATA_COUNT_WIDTH       (R_WR_DATA_COUNT_WIDTH),               //positive integer
      .PROG_FULL_THRESH          (20),               //positive integer
      .FULL_RESET_VALUE          (0),                //positive integer; 0 or 1
      .USE_ADV_FEATURES          ("0707"),           //string; "0000" to "1F1F"; 
      .READ_MODE                 ("fwft"),            //string; "std" or "fwft";
      .FIFO_READ_LATENCY         (0),                //positive integer;
      .READ_DATA_WIDTH           (R_DATAWIDTH),               //positive integer
      .RD_DATA_COUNT_WIDTH       (R_RD_DATA_COUNT_WIDTH),               //positive integer
      .PROG_EMPTY_THRESH         (10),               //positive integer
      .DOUT_RESET_VALUE          ("0"),              //string
      .CDC_SYNC_STAGES           (2),                //positive integer
      .WAKEUP_TIME               (0)                 //positive integer; 0 or 2;
    ) xpm_fifo_R_inst (
          .rst              (R_fifo_rst),//clk_domin : ui_clk
          .wr_clk           (ui_clk),
          .wr_en            (fdma_rvalid),
          .din              (fdma_rdata),
          .full             (),
          .overflow         (),
          .prog_full        (),
          .wr_data_count    (R_wcnt),
          .almost_full      (),
          .wr_ack           (),
          .wr_rst_busy      (R_wbusy),
          .rd_clk           (R_rclk_i),
          .rd_en            (R_rden_i),
          .dout             (R_data_o),
          .empty            (R_empty),
          .underflow        (),
          .rd_rst_busy      (),
          .prog_empty       (),
          .rd_data_count    (),
          .almost_empty     (),
          .data_valid       (),
          .sleep            (1'b0),
          .injectsbiterr    (1'b0),
          .injectdbiterr    (1'b0),
          .sbiterr          (),
          .dbiterr          ()
    );
  end
  else begin : FDMA_READ_DISABLE
    //禁用读使能，fdma总线赋0
    assign fdma_raddr   = 0;
    assign fdma_rareq   = 0;
    assign fdma_rsize   = 0;                                   	
    assign fdma_rdata   = 0;
    assign fdma_rready  = 0;
    assign fdma_rirq    = 0;	
    assign R_empty      = 0;
    assign R_data_o     = 0;
  end
endgenerate

endmodule

